Sub-2 nm Equivalent-Oxide-Thickness Ferroelectric Transistors for Cryogenic Memory and Computing.

Area of Science:

• Materials Science
• Solid State Physics
• Device Physics

Background:

• Ferroelectric hafnia-based field-effect transistors (FeFETs) are crucial for nonvolatile memory and in-memory computing.
• Their performance at deep-cryogenic temperatures (10 K) and scaled gate stacks is not well understood, especially in bulk silicon technology.

Purpose of the Study:

• To experimentally demonstrate the functionality of scaled FeFETs at cryogenic temperatures.
• To investigate the underlying mechanisms for robust operation and stability at 10 K.

Main Methods:

• Fabrication of front-end-of-line bulk silicon-channel FeFETs with sub-2 nm equivalent-oxide-thickness gate stacks.
• Electrical characterization at 10 K, including memory window, threshold voltage distribution, endurance, and retention tests.
• Correlative four-dimensional scanning transmission electron microscopy (4D STEM) for phase mapping.
• Implementation of a spiking neural network at 10 K for performance evaluation.

Main Results:

• Robust switching of FeFETs at 10 K with memory windows >1 V, low threshold voltage variation (std. dev. <40 mV), and endurance >10^7 cycles.
• Cryogenic wake-up increases the orthorhombic ferroelectric fraction, enhancing polarization stability and oxygen-metal coordination.
• Operational design window identified, with saturation of memory window beyond ±5 V programming voltages and 900 ns pulse widths.
• Spiking neural network achieved >92% accuracy on MNIST and 73.8% on NMNIST datasets at 10 K.

Conclusions:

• Scaled hafnia FeFETs exhibit excellent performance and stability at 10 K, driven by suppressed trapping and increased orthorhombic phase.
• These devices are suitable for energy-efficient cryogenic applications and integration into quantum-classical systems.
• Findings offer critical insights for materials and device design in extreme-temperature electronics.