ASIC-based Fetal Heart Rate Sensing System using Dry/Capacitive Electrodes

Fetal heart rate (fHR) monitoring is a critical tool for assessing fetal well-being. A home-use solution that enables comfortable and long-term monitoring is of great interest. Dry and capacitive abdominal electrodes are considered promising techniques for this purpose. However, prior systems are typically based on discrete components, whereas application-specific integrated circuit (ASIC) designs enable a smaller form factor, lower power consumption, and the ability to integrate advanced motion artifact effect reduction (MAR) techniques. This work proposes an ASIC-based system to address the limitations of prior discrete component designs.

A 16-channel recording ASIC with an integrated MAR technique was designed in 180nm CMOS. A prototype was developed using this IC, together with a wearable garment and an exemplary fHR extraction algorithm. The IC was electrically characterized, and the prototype was validated through both in-vitro and in-vivo experiments.

The chip achieves the required performance and MAR through a 10x extended dynamic range (>1 V) and saturation prevention, while occupying only 12.5 mm2 and consuming 450 μW. Validation with four pregnant volunteers using dry electrodes shows that within each 24-minute recording, at least 3 minutes of data provided sufficient quality for the detection of fetal QRS-peaks and fHR.

The IC-based solution offers low power, small form factor, MAR, and the ability to obtain fHR in real use cases.

The proposed design is the first IC-based solution for dry and potentially capacitive fHR monitoring, which proves to be a promising candidate for home monitoring applications.