Geometrical Design Schemes for the 2T0C DRAM Cell Using a Vertical Stack Transistor with a Distinctive Single IGZO...

In order to implement a three-dimensional (3D) 2-transistor-0-capacitor (2T0C) DRAM cell using a thermally sensitive InGaZnO (IGZO) channel, the impact of electrical interactions between the write transistor (WTr) and the read transistor (RTr) in a novel structure was investigated, and a control methodology was established. First, the adoption of a discrete active island pattern led to the suppression of parasitic channels. As a result, the subthreshold hump was eliminated, and an excellent subthreshold swing characteristic of 154.4 mV dec^-1 was achieved. Second, memory characterization revealed that electrical coupling effects resulting from parasitic capacitance and electrostatic effects in the 3D stacked structure compromise the storage node voltage (V_SN) charging efficiency. These can be attributed to the extended BE, which serves to reduce the device footprint, and the voltage applied to activate the RTr to read the V_SN value, respectively. Finally, the strategic placement of the asymmetric S/D electrodes in the vertical-channel thin-film transistor ensured excellent operational stability with an SN variation below 0.03 V after 1000 s. Consequently, long-term linear multilevel operation of 3 bits was achieved under various write operation conditions.