̀Nanoscale Additive Manufacturing of Sub-24 nm Spacing Silicon Nanowire Arrays and High-Performance GAA FET Based on...

Deploying gate-all-around (GAA) field effect transistors (FETs) in the back-end-of-line (BEOL) represents a promising pathway to extend Moore's law. Although the in-plane solid-liquid-solid (IPSLS) approach can produce planar silicon nanowires (SiNWs) with precise positions and alignment at low temperatures, the SiNW density should be further enhanced for higher integration density. Here, we employed SiO₂/SiN_x stacked multilayers to fabricate ultranarrow guiding steps with controllable widths of 30-75 nm via conventional lithography, followed by producing dense ordered SiNWs with diameters of 25.9 ± 2.0 nm, horizontal spacing of 21.3 ± 2.3 nm, and vertical spacing of <22 nm. Facilitated by the alumina sacrificial layer for SiNW suspension, high-performance GAA-FETs were successfully fabricated, demonstrating an I_on/I_off > 10⁷ and a steep subthreshold swing of ∼63.3 mV/dec. These results underscore the potential of IPSLS growth as a wafer-free additive manufacturing route in BEOL for monolithic 3D integration.