Predictive modeling of drain current in advanced FET architectures using ML-based TCAD calibration

The design and optimization of advanced semiconductor devices, such as multi gate MOSFETs, play a critical role in the miniaturization process of integrated circuits and the advancement of modern electronics. As device geometries shrink into the sub 10 nm region, accurate modeling and calibration of transistor behavior become increasingly essential yet computationally challenging. This study presents a machine learning (ML) driven predictive modeling approach that uses TCAD extracted datasets to accurately predict the drain current (I_d) of nanowire and nanoribbon FETs. Six ML models were trained and evaluated on TCAD data XGBoost, Random Forest, 1D Convolutional Neural Network (CNN), Multilayer Perceptron (MLP), Long Short-Term Memory (LSTM), and TabNet. Among all models, the ensemble methods XGBoost and Random Forest performed the best, with R² scores of 0.9926 and 0.9549 and RMSE values of 2.1 × 10⁻⁴ A and 2.0 × 10⁻⁴ A, respectively. These results were significantly better than the deep learning models LSTM (R² = 0.6778) and 1D CNN (R² = 0.6997). These results demonstrate that tree-based models can generalize more effectively for structured TCAD data, challenging the prevailing assumption that deep learning models universally perform better in device level prediction tasks. The proposed ML framework significantly reduces the need for iterative TCAD simulations, enabling rapid and accurate prediction of device behavior. As a novel contribution, a fully integrated web-based application has been developed to deploy the best performing models for real time I_d prediction and visualization.