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Electrically Reconfigurable Floating Gate Optoelectronic Synaptic Pixels For In-sensor Convolutional Image Feature Extraction With Built-in Contrast Enhancement.

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Electrically Reconfigurable Floating Gate Optoelectronic Synaptic Pixels For In-sensor Convolutional Image Feature Extraction With Built-in Contrast Enhancement.

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Electrically Reconfigurable Floating Gate Optoelectronic Synaptic Pixels for In-sensor Convolutional Image Feature

Md Sazzadur Rahman¹, Shahin Hashemkhani², Arijit Sarkar¹

¹Department of Electrical and Computer Engineering, Duke University, North Carolina, Durham 27708, United States.

|May 11, 2026

View abstract on PubMed

Summary

This summary is machine-generated.

Keywords:

2D materials analog in-memory computing circuit-device codesign contrast enhancement convolutional neural network (CNN)floating-gate FET optoelectronic synapse

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Researchers developed a novel optoelectronic synapse (OS) using molybdenum disulfide and graphene for in-pixel computing. This device enhances image contrast and performs convolutional operations, paving the way for efficient AI vision systems.

Area of Science:

Materials Science
Electrical Engineering
Computer Science

Background:

Conventional convolutional neural networks (CNNs) face energy and latency issues due to data transfer.
In-pixel computing with optoelectronic synaptic (OS) devices offers a solution but often lacks circuit-level integration.
Existing OS devices are device-centric, hindering scalable system implementation.

Purpose of the Study:

To develop a CMOS-compatible floating-gate optoelectronic synapse (FG-OS) for in-pixel computing.
To integrate device innovation with circuit codesign for enhanced image processing.
To demonstrate the feasibility of single-layer CNN architectures for intelligent vision.

Main Methods:

Developed a FG-OS using monolayer molybdenum disulfide (MoS2) and bilayer graphene.

Utilized a superlinear photoresponse for intrinsic image contrast enhancement.

Implemented fully electrical programming for low-voltage analog conductance modulation.

Designed a codesigned architecture for 4-bit information encoding with robustness.

Main Results:

Achieved high optical responsivity, even in low-light conditions.
Demonstrated intrinsic image contrast enhancement via superlinear photoresponse.
Successfully performed in-pixel convolutional operations like edge detection, sharpening, and blurring.
Showcased robust 4-bit information encoding against device variations.

Conclusions:

The FG-OS integrates device and circuit design for efficient in-pixel computing.
The device enables low-voltage, circuit-friendly analog operations, simplifying array implementation.
The developed FG-OS array offers a scalable pathway for in-sensor processing and single-layer CNNs.