Electrically Reconfigurable Floating Gate Optoelectronic Synaptic Pixels for In-sensor Convolutional Image Feature...

Area of Science:

• Materials Science
• Electrical Engineering
• Computer Science

Background:

• Conventional convolutional neural networks (CNNs) face energy and latency issues due to data transfer.
• In-pixel computing with optoelectronic synaptic (OS) devices offers a solution but often lacks circuit-level integration.
• Existing OS devices are device-centric, hindering scalable system implementation.

Purpose of the Study:

• To develop a CMOS-compatible floating-gate optoelectronic synapse (FG-OS) for in-pixel computing.
• To integrate device innovation with circuit codesign for enhanced image processing.
• To demonstrate the feasibility of single-layer CNN architectures for intelligent vision.

Main Methods:

• Developed a FG-OS using monolayer molybdenum disulfide (MoS2) and bilayer graphene.
• Utilized a superlinear photoresponse for intrinsic image contrast enhancement.
• Implemented fully electrical programming for low-voltage analog conductance modulation.
• Designed a codesigned architecture for 4-bit information encoding with robustness.

Main Results:

• Achieved high optical responsivity, even in low-light conditions.
• Demonstrated intrinsic image contrast enhancement via superlinear photoresponse.
• Successfully performed in-pixel convolutional operations like edge detection, sharpening, and blurring.
• Showcased robust 4-bit information encoding against device variations.

Conclusions:

• The FG-OS integrates device and circuit design for efficient in-pixel computing.
• The device enables low-voltage, circuit-friendly analog operations, simplifying array implementation.
• The developed FG-OS array offers a scalable pathway for in-sensor processing and single-layer CNNs.