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Related Concept Videos

Field Effect Transistor01:29

Field Effect Transistor

Field-effect transistors (FETs) are integral to electronic circuits and distinguished by their three-terminal setup: the gate, drain, and source. These transistors operate as unipolar devices, which utilize either electrons or holes as charge carriers, in contrast to bipolar transistors, which use both types of carriers. The primary function of the FET is to modulate the flow of these carriers from the source to the drain through a channel. The voltage difference between the gate and source...
MOSFET: Enhancement Mode01:22

MOSFET: Enhancement Mode

Enhancement-mode MOSFETs are pivotal components in electronics, distinguished by their capacity to act as highly efficient switches. They are part of the larger family of metal-oxide Semiconductor Field-Effect Transistors (MOSFETs). They are available in two types: p-channel and n-channel, each tailored to specific polarity operations.
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no current...
MOSFET01:16

MOSFET

The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) plays a pivotal role in modern electronics thanks to its versatility and efficiency in controlling electrical currents. This device, also known as IGFET, MISFET, and MOSFET, has three main terminals: the Source, Drain, and Gate. MOSFETs are classified into n-channel or p-channel types based on the doping characteristics of their substrate and the source or drain regions.
In an n-MOSFET, the structure includes n-type source and drain...
Biasing of FET01:22

Biasing of FET

Biasing a Junction Field Effect Transistor (JFET) is crucial for setting operational parameters and ensuring efficient functioning in electronic circuits. JFETs are characterized by using a single carrier type in N-channel or P-channel configurations, where the channel is surrounded by PN junctions. These junctions are central to the device's ability to control current flow.
In an N-channel JFET, the structure consists of N-type material forming the channel on a P-type substrate, with the gate...
Types of Semiconductors01:20

Types of Semiconductors

Intrinsic semiconductors are highly pure materials with no impurities. At absolute zero, these semiconductors behave as perfect insulators because all the valence electrons are bound, and the conduction band is empty, disallowing electrical conduction. The Fermi level is a concept used to describe the probability of occupancy of energy levels by electrons at thermal equilibrium. In intrinsic semiconductors, the Fermi level is positioned at the midpoint of the energy gap at absolute zero. When...
Metal-Semiconductor Junctions01:24

Metal-Semiconductor Junctions

The contact of metal and semiconductor can lead to the formation of a junction with either Schottky or Ohmic behavior.
Schottky Barriers
Schottky barriers arise when a metal with a work function (Φm) contacts a semiconductor with a different work function (Φs). Initially, electrons transfer until the Fermi levels of the metal and semiconductor align at equilibrium. For instance, if Φm > Φs, the semiconductor Fermi level is higher than the metal's before contact. The semiconductor's...

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Related Experiment Video

Updated: May 15, 2026

Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon
06:57

Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon

Published on: July 17, 2020

Interface Engineering and Substitutional Doping in In2Ge2Te6 for High-Performance 2D p-Type FETs and CMOS Devices.

Tong Zhao1, Jialin Yang1, Tingting Guo1

  • 1MIIT Key Laboratory of Advanced Display Materials and Devices, Jiangsu Engineering Research Center for Quantum Dot Display, Institute of Optoelectronics & Nanomaterials, School of Materials Science and Engineering, Nanjing University of Science and Technology, Nanjing, China.

Small (Weinheim an Der Bergstrasse, Germany)
|May 14, 2026
PubMed
Summary
This summary is machine-generated.

Optimizing metal contacts for 2D semiconductors like In2Ge2Te6 significantly boosts device performance. This study reduced Schottky barriers and contact resistance, enhancing 2D p-type field-effect transistors (FETs) and CMOS devices.

Keywords:
CMOSIn2Ge2Te6field‐effect transistorsinterface engineeringsubstitutional doping

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Fabrication of Schottky Diodes on Zn-polar BeMgZnO/ZnO Heterostructure Grown by Plasma-assisted Molecular Beam Epitaxy
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Fabrication of Schottky Diodes on Zn-polar BeMgZnO/ZnO Heterostructure Grown by Plasma-assisted Molecular Beam Epitaxy

Published on: October 23, 2018

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
07:12

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

Published on: August 28, 2018

Related Experiment Videos

Last Updated: May 15, 2026

Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon
06:57

Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon

Published on: July 17, 2020

Fabrication of Schottky Diodes on Zn-polar BeMgZnO/ZnO Heterostructure Grown by Plasma-assisted Molecular Beam Epitaxy
14:16

Fabrication of Schottky Diodes on Zn-polar BeMgZnO/ZnO Heterostructure Grown by Plasma-assisted Molecular Beam Epitaxy

Published on: October 23, 2018

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
07:12

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

Published on: August 28, 2018

Area of Science:

  • Materials Science
  • Semiconductor Physics
  • Nanotechnology

Background:

  • Metal-semiconductor interfaces are critical for 2D semiconductor device performance, impacting charge carrier injection efficiency.
  • High-performance contacts for emerging 2D semiconductors, particularly p-type materials, face challenges like Fermi-level pinning and defect scattering, leading to increased contact resistance.
  • These interface issues create parasitic barriers that limit the operational efficiency of p-type devices.

Purpose of the Study:

  • To investigate the combined effects of interface contact and doping engineering on optimizing the performance of the low effective mass p-type semiconductor In2Ge2Te6.
  • To systematically explore strategies for reducing Schottky barrier height and contact resistance in 2D p-type field-effect transistors (FETs).
  • To demonstrate the application of these strategies in fabricating high-performance 2D complementary metal oxide semiconductor (CMOS) devices.

Main Methods:

  • Systematic exploration of interface contact and doping engineering on In2Ge2Te6.
  • Introduction of optimized electrodes and region-selective oxygen doping.
  • Characterization of Schottky barrier height and contact resistance reduction.
  • Fabrication and testing of an In2Ge2Te6/MoS2 CMOS device.

Main Results:

  • Reduced Schottky barrier height from 63 to 36 meV.
  • Decreased contact resistance from 1.3 to 0.6 kΩ·µm.
  • Achieved a voltage gain of 140 in an In2Ge2Te6/MoS2 CMOS device with low static power consumption (2.9 nW at 1 V).

Conclusions:

  • Optimized electrode work function and impurity band creation effectively reduce contact barriers in 2D p-type semiconductors.
  • The developed strategy offers a straightforward approach to enhance the performance of 2D p-type FETs and CMOS devices.
  • This work paves the way for improved electronic devices based on emerging 2D materials.