Monolithic integration of p- and n-type doped 2D WSe₂ for wafer-scale complementary logic circuits

Atomically thin two-dimensional (2D) semiconductors are promising candidates for next-generation electronics, which could effectively suppress short-channel effects and consequently reduce static power consumption. However, the lack of effective doping methods for 2D semiconductors remains a significant challenge, impeding the realization of homogeneous complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs). Here, we report the monolithic integration of wafer-scale homogeneous top-gated WSe₂ CMOS circuit arrays. The p-type and n-type doping methods could effectively modulate carrier polarity and concentration for WSe₂, enabling the fabrication of wafer-scale CMOS inverter arrays via a proposed bilayer hard mask process. A representative CMOS inverter exhibits a voltage gain of up to 396 V/V, with a low static power consumption of ~ 30 pW and a noise margin exceeding 90%. Furthermore, more complex CMOS circuits, like XOR and a multiplexer (MUX), are successfully fabricated. This demonstration of homogeneous CMOS integration shows a promising strategy for the practical deployment of 2D semiconductors in low-power large-scale ICs.