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Related Concept Videos

iChip01:24

iChip

The cultivation of environmental microorganisms has long been hindered by the inability to replicate complex native conditions in vitro. The isolation chip (iChip) addresses this limitation by facilitating the growth of previously uncultivable microorganisms through in situ incubation. Designed for high-throughput microbial cultivation, the iChip comprises hundreds of microchambers, each capable of housing a single microbial cell. These microchambers are loaded with a mixture of molten agar and...
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State Space Representation01:27

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Updated: May 28, 2026

A Microfluidic Chip for ICPMS Sample Introduction
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Published on: March 5, 2015

SpChipADF: An Architecture Design Framework for Radar Signal Processing Hardware Accelerators.

Huan Wang1,2, Shu Yang1,2, Zhen Chen1,2

  • 1National Key Laboratory of Microwave Imaging Technology, Aerospace Information Research Institute, Chinese Academy of Sciences, Beijing 100190, China.

Micromachines
|May 27, 2026
PubMed
Summary
This summary is machine-generated.

This study introduces a novel hardware accelerator design framework for Unmanned Aerial Vehicles (UAVs). It optimizes signal processing for edge computing, significantly reducing resource usage and enhancing energy efficiency for payloads.

Keywords:
SAR imagingSWaPUAVsalgorithm-hardware co-designedge-side signal processingreconfigurable architecture

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Time Multiplexing Super Resolving Technique for Imaging from a Moving Platform
06:25

Time Multiplexing Super Resolving Technique for Imaging from a Moving Platform

Published on: February 12, 2014

Area of Science:

  • Electrical Engineering
  • Computer Engineering
  • Aerospace Engineering

Background:

  • Lightweight Unmanned Aerial Vehicles (UAVs) face significant Size, Weight, and Power (SWaP) constraints.
  • Traditional Application-Specific Integrated Circuit (ASIC) designs struggle with the low latency and resource demands of edge-side signal processing.

Purpose of the Study:

  • To propose a novel signal processing hardware accelerator architecture design framework for UAV payloads.
  • To address the challenges of designing efficient edge-side signal processing architectures under strict SWaP limitations.

Main Methods:

  • Algorithm-hardware co-design framework utilizing cross-level dataflow graph representation.
  • Systematic construction of reconfigurable dataflow templates and reusable operator IP components.
  • Multi-objective design space exploration for Pareto-optimal mapping and automatic hardware description generation for FPGA prototyping.

Main Results:

  • Achieved a 51.4% reduction in equivalent gate count for Synthetic Aperture Radar (SAR) imaging compared to non-reconfigurable architectures, without increasing processing latency.
  • Improved energy efficiency by 25.4% (from 12.8 MS/J to 16.0 MS/J) compared to conventional reconfigurable dataflow architectures.
  • Enabled a 4x scaling of supported data processing size, offering a high-performance and scalable solution.

Conclusions:

  • The proposed framework provides an effective solution for high-performance, scalable hardware acceleration in lightweight edge-side computing platforms for UAVs.
  • Algorithm-hardware co-design is crucial for overcoming SWaP constraints in UAV payload processing.
  • The framework facilitates rapid prototyping and validation, accelerating the development of advanced UAV applications.