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Published on: October 23, 2018
An FPGA-Based Event-Timing Front-End for Time-Resolved Sensing with Dual-Mode Experimental Characterization
Juan Núñez1, Rafaella Fiorelli1
1Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla), Américo Vespucio 28, 41092 Sevilla, Spain.
Sensors (Basel, Switzerland)
|May 27, 2026
Summary
This FPGA-based timing front-end offers reliable event detection for time-resolved sensing. It balances performance and data export, providing a practical solution for asynchronous workflows.
Area of Science:
- Electronics Engineering
- Instrumentation
- Digital Systems
Background:
- Time-resolved sensing and event-driven measurements require precise timing.
- Existing systems face challenges with event trustworthiness, dead-time, and data readout.
Purpose of the Study:
- To present an FPGA-based timing front-end for detector-independent use.
- To evaluate its performance in asynchronous time-resolved sensing workflows.
Main Methods:
- Implemented a timing subsystem with carry-chain interpolation and timestamp formation.
- Validated using internal ILA and external UART-based experiments.
- Assessed event quality, dead-time handling, and host-visible export.
Main Results:
- Identified a safe operating point for export-compatible data acquisition.
- Characterized a high-rate regime and the transition between modes.
- Demonstrated practical behavior without catastrophic degradation across frequencies.
Conclusions:
- The FPGA timing front-end is a practical, experimentally characterized subsystem.
- It offers interpretable behavior in internal and export-visible operating regimes.
- Suitable for asynchronous workflows like single-photon avalanche diode (SPAD) sensing.
