Monolithic three-dimensional integration of silicon transistors.

Area of Science:

• Materials Science and Engineering
• Electrical Engineering
• Nanotechnology

Background:

• Monolithic three-dimensional (3D) integrated circuits offer enhanced density, reduced power consumption, and increased bandwidth.
• Existing back-end-of-line-compatible transistors on top tiers exhibit inferior performance compared to bottom-tier silicon metal-oxide-semiconductor field-effect transistors (MOSFETs).
• This performance gap limits the full potential of monolithic 3D integration.

Purpose of the Study:

• To develop a scalable fabrication method for high-performance transistors suitable for monolithic 3D integrated circuits.
• To enable the sequential fabrication of multi-tier complementary junctionless transistors on a single substrate.
• To achieve transistor performance comparable to front-end-of-line silicon MOSFETs within a limited thermal budget.

Main Methods:

• Utilized uniformly doped, ultrathin (≤10 nm) single-crystalline silicon nanomembranes.
• Employed a scalable roll-transfer-printing process compatible with wafer-scale production and tolerant to substrate variations.
• Sequentially fabricated complementary junctionless transistors at processing temperatures ≤400°C.

Main Results:

• Achieved transistor performance approaching that of front-end-of-line silicon MOSFETs, with current density > 650 µA/µm.
• Demonstrated sub-10 nm inter-tier registration for high-density vertical integration.
• Successfully constructed functional logic gates (inverters, NAND, NOR) and static random-access memory (SRAM) cells using up to three-tier integration.

Conclusions:

• The developed roll-transfer-printing process enables the fabrication of high-performance, vertically stacked silicon transistors.
• This method provides a viable pathway for creating silicon-based monolithic 3D integrated circuits.
• The technology is particularly promising for research and low-volume prototyping of advanced integrated circuits.