A 40 GSample/s (GSPS), 13 GHz bandwidth time-interleaved analog-to-digital converter (TIADC) system with...

Data acquisition systems based on the time-interleaved analog-to-digital converter (TIADC) parallel sampling architecture offer an effective solution to overcome the performance limitations of single-chip analog-to-digital converters (ADCs), addressing the growing demand for signal bandwidth multiplication in applications such as wideband receivers and high-end electronic test instruments. However, mismatches in sampling time, gain, and offset among sub-ADCs within the TIADC system, coupled with frequency response distortion, i.e., amplitude frequency distortion (AFD) and phase frequency distortion (PFD), in the analog front end, pose significant challenges to system performance. These non-idealities adversely affect both dynamic performance and signal reconstruction accuracy. This paper presents a statistics-based estimation algorithm for TIADC mismatch errors and designs a digital finite impulse response filter capable of arbitrary frequency response to jointly compensate AFD and PFD. The proposed method is validated on a hardware system operating at 40 GSample/s with a 13 GHz bandwidth. Experimental results demonstrate a 15 dB improvement in system signal-to-noise ratio (SNR), a post-compensation amplitude frequency response fluctuation of 0.98 dB, and an enhanced rise time of 38.51 ps for the step signal with a 13 GHz bandwidth.