System-level FPGA validation of a trainable and robust multiplier-free spiking neural network

The growing scale of artificial intelligence models has expanded their impact, yet efficient deployment on hardware remains challenging due to intensive matrix-based computation and energy demand. Spiking neural networks (SNNs), inspired by biological neural processing, offer an event-driven and energy-efficient alternative for neuromorphic computing. In this work, we present a system-level FPGA validation of a trainable, multiplier-free SNN that supports on-chip supervised learning under fixed-point constraints. By implementing a sensitive-noise threshold (SNT) mechanism and a limited remote supervised method (LReSuMe) on a Xilinx ZCU104 FPGA platform, the proposed design achieves high throughput, low power consumption, and preserved robustness to the noise. Weight visualization further indicates structured and interpretable learning behavior, supporting the reliability of hardware-based neuromorphic systems.