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Accelerating Active Learning for Image Classification Through FPGA-Based Implementation.

Angelo Barbieri1, Christopher A Flores2, Wladimir Valenzuela3

  • 1Department of Electrical Engineering, Universidad de Concepción, Concepción 4070386, Chile.

Sensors (Basel, Switzerland)
|June 26, 2026
PubMed
Summary
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This study introduces a hardware-accelerated method for active learning (ALrn) in image classification. It significantly speeds up sample selection for deep neural networks (DNNs) on embedded systems while reducing power consumption.

Area of Science:

  • Computer Vision
  • Machine Learning
  • Hardware Acceleration

Background:

  • Deep Neural Networks (DNNs) excel at image classification but demand substantial data and resources, hindering embedded system deployment.
  • Active Learning (ALrn) mitigates labeling needs by selecting informative samples, yet its computational demands, especially for high-dimensional data, pose challenges.
  • Efficient instance selection is crucial for deploying ALrn in resource-constrained environments.

Purpose of the Study:

  • To develop a hardware-accelerated approach for the instance selection stage in uncertainty-based ALrn for image classification.
  • To reduce the computational and memory requirements of ALrn's query strategy for high-dimensional images.
  • To enable efficient ALrn on embedded systems by optimizing the sample selection process.

Main Methods:

Keywords:
FPGA accelerationactive learningembedded sensorsimage classificationmargin samplingtop-k selection

Related Experiment Videos

  • A novel in-line top-k selection algorithm was designed to avoid sorting and minimize resource usage.
  • The algorithm was implemented on a Field Programmable Gate Array (FPGA) accelerator integrated with an Advanced RISC Machine (ARM) processor on a Xilinx ZYNQ-7000 System on Chip (SoC).
  • The system utilized the Python Productivity for Zynq (PYNQ) framework for data handling and communication.

Main Results:

  • The hardware accelerator achieved significant speedups of 231.7× and 22.9× over software baselines for query-strategy computation.
  • The system demonstrated negligible performance deviation in learning curves compared to software-only methods on diverse datasets.
  • The accelerator operated at a low power consumption of 0.473 W, outperforming conventional CPU and GPU platforms.

Conclusions:

  • The proposed FPGA-based accelerator offers an efficient and low-power solution for instance selection in ALrn for image classification.
  • The approach is effective in reducing the computational cost of ALrn, making it suitable for embedded systems.
  • The demonstrated efficiency and extensibility suggest broad applicability across various ALrn strategies and hardware platforms.