An integrated framework TSV-INet for arbitrarily distributed TSV interposer wafer warpage simulation.

Area of Science:

• Materials Science
• Mechanical Engineering
• Artificial Intelligence

Background:

• Through-silicon vias (TSVs) are critical for advanced semiconductor packaging.
• TSV-induced wafer warpage negatively impacts manufacturing yield.
• Accurate, fast warpage simulation during the design phase is essential.

Purpose of the Study:

• To develop a hybrid AI framework for predicting TSV-induced warpage.
• To enable efficient wafer-level warpage simulation using RVE homogenization.
• To investigate the impact of TSV layout and density on thermo-mechanical behavior.

Main Methods:

• A hybrid framework (CNN + GNN) named TSV-INet was developed.
• TSV representative volume elements (RVEs) were used to predict anisotropic effective properties.
• RVE-based finite element homogenization enabled wafer-level warpage simulation.
• Pixel-level encoding and topology-aware message passing were employed.

Main Results:

• TSV-INet demonstrated improved data efficiency and robustness for unseen TSV layouts.
• For non-extreme layouts, redistribution had limited global warpage impact but affected local stress.
• Increased TSV density significantly amplified wafer warpage and altered deformation modes.

Conclusions:

• The TSV-INet framework provides a practical tool for warpage prediction in TSV interposers.
• TSV density is a primary driver of wafer warpage.
• Findings offer guidance for warpage-aware and stress-aware TSV interposer design.