Related Experiment Video
Updated: Jul 4, 2026
Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities
Published on: July 24, 2015
Wafer-scale robust graphene electronics under industrial processing conditions
E P van Geest1,2, B S Can1,2, M Makurat1,2
1Leiden Institute of Chemistry, Leiden University, Einsteinweg 55, 2333CC, Leiden, The Netherlands. g.f.schneider@chem.leidenuniv.nl.
None:
When commercial grade electronic devices contain nanomaterials like graphene, it is crucial that these materials resist industrial processes and harsh environments. For environments that contain water, graphene delamination due to intercalation is a notorious problem. This renders graphene incompatible with key wafer-processing steps in the semiconductor industry. In this work, a covalent pyrene-based adhesion layer is synthesized in a facile, two-step procedure. Through π-π interactions, the adhesion of graphene to silicon wafers was maintained under harsh processing conditions, i.e. acidic and alkaline solutions, several organic solvents, and sonication. Moreover, devices were produced with a measurement yield up to 99.7% and reproducible device-to-device electronic performance on 4-inch silicon wafers.
