Related Experiment Video
Updated: Jul 9, 2026
14:16
Fabrication of Schottky Diodes on Zn-polar BeMgZnO/ZnO Heterostructure Grown by Plasma-assisted Molecular Beam Epitaxy
Published on: October 23, 2018
Bridging the p-type gap in oxide electronics with 2D semiconductors.
Taikyu Kim1, Seokhyun Hwang2, Jae Kyeong Jeong3
1Department of Electrical Engineering, Stanford University, Stanford, CA, USA.
Communications Engineering
|July 7, 2026
Summary
Monolithic 3D integration using 2D semiconductors enables denser, more energy-efficient chips. This review explores pathways for high-performance 2D p-channel transistors essential for advanced computing systems.
Area of Science:
- Materials Science
- Electrical Engineering
- Semiconductor Physics
Background:
- Monolithic three-dimensional (3D) integration, placing logic and memory in the back-end-of-line (BEOL), is crucial for advancing AI, cloud, and edge computing.
- Complementary metal-oxide-semiconductor (CMOS) technology in BEOL requires pairing p-type and n-type transistors.
Purpose of the Study:
- To review manufacturing-aligned strategies for developing high-performance 2D p-channel transistors.
- To assess the feasibility of integrating 2D p-type semiconductors into monolithic 3D BEOL CMOS.
Main Methods:
- Assessment of transfer-free, low-temperature growth techniques for 2D materials.
- Evaluation of methods for achieving clean van der Waals contacts.
- Analysis of p-doping strategies and mitigation of material degradation (crystallization, volatility, interdiffusion).
Main Results:
- Identified key challenges in 2D p-channel transistor fabrication, including doping and material stability.
- Examined recent demonstrations of gain-cell and vertical complementary field-effect transistors (CFETs).
Conclusions:
- Achieving manufacturable, high-performance 2D p-type semiconductors is critical for dense, low-power monolithic 3D chips.
- Further research into controlled growth, doping, and interface engineering is necessary for practical BEOL integration.
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