Ultra-High Gain Vertically Stacked WS2 NMOS Inverter Enabled by Co-Optimization of Layer Number and Contact Metal

Area of Science:

• Materials Science
• Nanotechnology
• Semiconductor Devices

Background:

• Multilayer two-dimensional (2D) transition-metal dichalcogenides (TMDCs) offer enhanced electronic properties over monolayers.
• Challenges exist in large-area synthesis and device fabrication of multilayer TMDCs.

Purpose of the Study:

• To optimize large-area multilayer WS₂ field-effect transistors (FETs) for improved performance.
• To investigate the impact of channel layer thickness and contact metals on device characteristics.
• To demonstrate high-performance vertically stacked inverters using optimized WS₂ FETs.

Main Methods:

• Sequential stacking of chemical vapor deposition (CVD)-grown monolayer WS₂.
• Engineering of channel layer thickness (trilayer WS₂ identified as optimal).
• Optimization of source/drain contact metals (Au electrodes selected for stability and low contact resistance).

Main Results:

• Trilayer WS₂ FETs demonstrated an optimal balance between conductivity and interlayer transport.
• Gold (Au) contacts exhibited superior chemical stability and reduced barrier formation.
• A large-area vertically stacked NMOS inverter using optimized 3L WS₂ (driver) and 1L WS₂ (load) FETs was successfully fabricated.
• The inverter achieved a record-high voltage gain compared to existing architectures.

Conclusions:

• Combined engineering of WS₂ channel thickness and contact metals is crucial for high-performance devices.
• This approach enables scalable, area-efficient 3D integration using large-area 2D TMDCs.
• The demonstrated vertically stacked inverter represents a significant step towards advanced integrated circuits.