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RISC-V-based YOLOv3-tiny acceleration with runtime-reconfigurable systolic arrays and custom instructions
Shuya Wang1, Xuecong Chen2, Detao Nie3
1Tongda College, Nanjing University of Posts and Telecommunications, Yangzhou, 225127, China. wangsyz@njupt.edu.cn.
Scientific Reports
|July 21, 2026
Summary
This study introduces a RISC-V acceleration framework for YOLOv3-tiny object detection on edge devices. The novel architecture significantly reduces computation time and speeds up inference on resource-constrained platforms.
Area of Science:
- Computer Engineering
- Embedded Systems
- Artificial Intelligence
Background:
- YOLOv3-tiny is crucial for edge object detection but faces computational and flexibility challenges on constrained platforms.
- Conventional processors limit the deployment of YOLOv3-tiny due to high computational demands.
Purpose of the Study:
- To develop a RISC-V-based acceleration framework for efficient YOLOv3-tiny inference on edge devices.
- To enhance YOLOv3-tiny deployment on resource-constrained platforms through a novel CPU-accelerator architecture.
Main Methods:
- Integrated a Hummingbird E203 core with a dedicated accelerator using the NICE interface.
- Introduced 11 custom instructions for data movement, convolution control, and post-processing.
- Implemented a runtime-reconfigurable systolic array and specialized modules on an Artix-7 FPGA.
Main Results:
- Achieved a 79.5% reduction in convolution execution time and a 4.89x speed-up over baseline RISC-V.
- Reduced cycle costs for sorting (60.55%) and IoU computation (45.44%) via hardware-supported post-processing.
- Demonstrated significant performance gains for YOLOv3-tiny inference on edge platforms.
Conclusions:
- The proposed processor-coupled acceleration architecture effectively addresses YOLOv3-tiny inference challenges on edge devices.
- Runtime-reconfigurable hardware and custom instructions are key to optimizing performance for resource-constrained object detection.
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