Integration of Reconfigurable p-Bit and 1R Crossbar Array for Memristive Probabilistic Computing

Area of Science:

• Emerging computing paradigms
• Materials science in electronics
• Computational complexity

Background:

• Probabilistic computing offers an efficient approach for high-dimensional problems and combinatorial optimization.
• Energy-based models, defined by interaction (J) matrices and bias (h) vectors, are key to mapping these problems.
• Hardware implementations often face challenges in representing these parameters and achieving stochastic updates.

Purpose of the Study:

• To present a novel memristive probabilistic computing system.
• To demonstrate a hardware framework for solving combinatorial optimization problems (COPs).
• To validate the system's functionality, scalability, and generality.

Main Methods:

• Integration of volatile memristors as probabilistic bits (p-bits) for stochastic updates.
• Utilization of non-volatile memristors in a selector-less 1R crossbar array (CBA) for J matrix and h vector representation.
• Experimental validation using reversible logic gates (AND, NAND) and simulation of a 2-bit binary multiplier.

Main Results:

• Demonstrated successful reversible AND and NAND gate operations in both forward and inverse modes.
• Volatile memristors enabled reconfigurable probabilistic outputs via stochastic filament dynamics.
• Non-volatile memristors facilitated reliable CBA operation without selectors.
• Simulations confirmed the architecture's scalability and generality for complex operations.

Conclusions:

• The proposed memristive system provides a practical and scalable framework for fully hardware-based probabilistic computing.
• This architecture leverages unique properties of volatile and non-volatile memristors for efficient computation.
• The work paves the way for advanced memristive solutions in solving complex computational challenges.