An efficient serialized hardware implementation of the ASCON algorithm

Area of Science:

• Cryptography and Hardware Security
• Embedded Systems Design
• Internet of Things (IoT) Security

Background:

• The Internet of Things (IoT) era presents significant hardware and data transfer security challenges.
• Lightweight Cryptography (LWC) algorithms are essential for resource-constrained IoT applications.
• Existing solutions often struggle to meet stringent power and area limitations.

Purpose of the Study:

• To present a hardware implementation of the ASCON-128 Lightweight Cryptography algorithm.
• To optimize the design for IoT applications and edge devices with strict power and area constraints.
• To evaluate the performance and efficiency of the ASCON-128 implementation on both FPGA and ASIC.

Main Methods:

• A serialized hardware architecture was utilized to minimize logic usage and resource footprint.
• The design employs a sponge-based construction in authenticated mode to maintain throughput.
• Performance was evaluated on an ultra-low-power Lattice iCE40 FPGA and a 16nm TSMC FinFET ASIC.

Main Results:

• FPGA implementation on Lattice iCE40 achieved 228.8 MHz Fmax using 582 LUTs and 2.28 mW power.
• ASIC implementation (16nm TSMC FinFET) consumed 0.254 mW power with an area of 1.341 kGE.
• Achieved energy efficiency of 0.106 nJ/bit and throughput of 2.381 Mbps at 100 MHz on ASIC.

Conclusions:

• The proposed ASCON-128 hardware architecture effectively addresses security needs for low-power IoT and RFID applications.
• The design demonstrates a favorable balance between security, performance, and resource utilization.
• This implementation offers a viable solution for securing data in power-sensitive and area-constrained environments.