A reconfigurable hardware infrastructure for evaluating PUFs in non-volatile memories

Area of Science:

• Hardware security and applied cryptography.
• Integrated circuit design and testing.
• Non-volatile memory characterization.

Background:

• Physical Unclonable Functions (PUFs) leverage unique hardware manufacturing variations for secure cryptographic key generation.
• Memory modules offer a cost-effective source for PUF-based key extraction.
• Existing PUF extraction techniques include row hammering and exploiting memory timing variations.

Purpose of the Study:

• To introduce a dedicated measurement ecosystem for performing PUF experiments on various memory modules, particularly novel non-volatile types.
• To enable dynamic control over experimental parameters like voltage and timing specifications.
• To facilitate the scheduling, retrieval, storage, and evaluation of PUF experiment results.

Main Methods:

• Development of a custom Printed Circuit Board (PCB) for connecting diverse memory types to reconfigurable hardware.
• Deployment of an optimized hardware design on a Field-Programmable Gate Array (FPGA) for executing PUF experiments.
• Implementation of a software program for experiment scheduling, result retrieval, and data management.

Main Results:

• The proposed system successfully enables PUF experiments on various memory modules.
• Dynamic adjustment of voltage and timing specifications during experiments is achieved.
• A comprehensive framework for PUF data acquisition and analysis is established.

Conclusions:

• The presented measurement ecosystem provides a flexible and powerful platform for PUF research on memory modules.
• This work facilitates the exploration of novel PUF extraction techniques and enhances hardware security applications.
• The developed system supports the reliable generation and evaluation of cryptographic keys derived from hardware variations.