Dual-material-gate engineering for GIDL suppression and pillar aspect-ratio reduction in 4F²vertical DRAM cell...

A key scaling challenge in 4F²vertical DRAM cell transistors is that gate-induced drain leakage (GIDL) suppression conventionally requires a long lightly doped drain (LDD) region, which increases the vertical pillar height and exacerbates the pillar aspect-ratio constraint. This work proposes a dual-material-gate (DMG) architecture as an electrostatic alternative to LDD extension for GIDL control. By introducing an M1-M2-M1 gate configuration, the proposed structure redistributes the channel potential near the storage-node-side gate edge, relaxes local band bending, and reduces the peak electric field responsible for band-to-band tunneling leakage. Calibrated TCAD simulations demonstrate that the DMG structure enables the LDD length to be reduced from 13 to 7 nm while maintaining nearly identical OFF-state current. Consequently, the total pillar height is reduced from 60 to 48 nm, corresponding to a 20% reduction. The shortened LDD also enhances current drivability and improves write recovery time, while the optimized DMG design achieves a retention time of 34.5 s and provides a practical, process-tolerant design window. These results indicate that DMG-based electrostatic gate engineering can decouple GIDL suppression from LDD extension, thereby improving the structural feasibility of 4F²vertical DRAM cell transistors.