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Updated: Aug 25, 2026

Analysis of Contact Interfaces for Single GaN Nanowire Devices
Published on: November 15, 2013
Extracting transfer length and scaling down contact electrodes in InAs nanowire transistors
Yi-Fan Jiang1, Xin-Yue Li1, Meng-Lan Li2
1Key Laboratory for the Physics and Chemistry of Nanodevices, School of Electronics, Peking University, Beijing 100871, China. qingchen@pku.edu.cn.
None:
Facing the future scaling limit of silicon-based complementary metal-oxide-semiconductor (CMOS), the scaling potential of novel materials and devices in Beyond Moore technology solutions needs to be evaluated. In addition to scaling the channel length and gate length, scaling the contact length is also essential. Here, we investigate the contact electrode scaling in InAs nanowire transistors. Utilizing the transfer length method (TLM) and the four-probe method, we determine the scaling limit for the contact electrodes (the transfer length, LT) to be 238 and 131 nm, respectively. Importantly, we develop an asymmetric contact-based method to extract LT by directly comparing on-state performance before and after swapping the asymmetric source and drain electrodes in InAs nanowire transistors. Notably, we find that the scaling limits of the source and drain electrodes differ distinctly, with an LT of 30-50 nm for the source electrode and below 30 nm for the drain electrode. Our results indicate the inaccuracy of the TLM and the four-probe method. Based on the above results, an extremely narrow InAs nanowire transistor with the device width being only 240 nm is fabricated. The transistor has superior subthreshold performance and a smaller footprint than that of n-type transistors in the Si 90 nm technology node. Our method and results are helpful for guiding the scaling process of InAs nanowire transistors and other transistors.
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