Ga2O3-Engineered Buried-Channel Transport in Amorphous IGZO Thin-Film Transistors with Improved Mobility and...

Amorphous In-Ga-Zn-O (IGZO) thin-film transistors (TFTs) are promising channel candidates for future DRAM cell transistors because of their ultralow off-state leakage, moderate mobility, low-temperature processability, and compatibility with conformal atomic layer deposition (ALD). However, the n-type nature of IGZO commonly leads to negative threshold voltage (Vth), which is unfavorable for DRAM cells that must maintain a low-leakage off state for long retention. In addition, mobility enhancement by increasing the In contribution or reducing Ga content generally pushes Vth further negative and degrades bias-stress reliability. Here, we report a co-designed Ga2O3/IGZO buried-channel stack that mitigates the trade-off among field-effect mobility (µFE), Vth, and bias-stress reliability. Across Devices 1-4, the designed gate-side Ga2O3 thickness, lower-IGZO thickness, and lower-IGZO composition were co-varied to maintain an approximately constant total semiconductor thickness and a positive Vth near 0.8-1.0 V. The optimized Device 3 with a designed 1.5 nm Ga2O3 region exhibited a median µFE of 14.6 ± 0.43 cm2 V-1 s-1, compared with 7.7 ± 0.39 cm2 V-1 s-1 for Device 1, while retaining a median Vth of 0.852 ± 0.020 V (n = 10 TFTs per stack). Separate reliability measurements showed a representative increase in constant-voltage-stress time-to-breakdown from 153 to 7890 s and a 27% lower mean PBTS-induced ΔVth for Device 3 than Device 1 at 104 s and 403 K (0.572 versus 0.786 V; n = 3 each). Structural, chemical, capacitance, and temperature-dependent transport analyses show that the 300 °C O2 anneal and 450 °C Al2O3 gate-dielectric ALD step convert the initially inserted Ga2O3/IGZO bilayer into a partially intermixed gate-side channel. A STEM-EDS-constrained, self-consistent one-dimensional Poisson analysis further shows that In redistribution shifts the calculated charge centroid and carrier-density maximum away from the Al2O3 interface at equal mobile sheet density. Together, these results support a displaced, depth-distributed buried channel that reduces exposure to the trap-sensitive dielectric interface while preserving effective gate control and high-temperature off-state margin.