Cryogenic Imaging Enabled by the Graphene-Silicon Heterojunction Array
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Updated: Oct 25, 2026

Application of Monolayer Graphene to Cryo-Electron Microscopy Grids for High-resolution Structure Determination
Published on: November 10, 2023
Ming Lu1,2, Sihao Wang3, Yinnan Zhang1
1College of Civil Engineering and Architecture, Zhejiang University, Hangzhou310058, P. R. China.
Abstract:
Cryogenic imaging is essential for applications in space exploration, quantum science, and biomedicine. However, extending cryogenic photodetectors into imaging arrays remains challenging due to the lack of reliable readout mechanisms and effective crosstalk suppression at temperatures below 4 K. Conventional imaging technologies, including charge-coupled devices (CCDs), complementary metal-oxide-semiconductor (CMOS) image sensors, and CMOS-based readout integrated circuits (ROICs), rely on carrier transport and transistor operation that degrade under cryogenic conditions, while superconducting approaches face challenges in scaling and high-speed operation due to wiring complexity and readout constraints. Here, we report a transistor-free, row-column addressable imaging architecture based on graphene-silicon heterojunction arrays, in which the imaging plane consists solely of heterojunction pixels without auxiliary electronic components. Owing to the intrinsic self-blocking effect, the device achieves effective crosstalk suppression and stable imaging at both room temperature (293 K) and cryogenic conditions (3 K). Furthermore, the pronounced suppression of dark current at cryogenic temperatures substantially enhances weak-light sensitivity, enabling imaging at illumination levels nearly 2 orders of magnitude lower than those required at room temperature. This work presents a transistor-free imaging architecture with intrinsic crosstalk suppression, enabling scalable array readout at cryogenic temperatures and providing a promising route toward large-scale, high-density low-temperature imaging.

