Quantized Analog Inference Hardware Enabled by MoS_2-Hf_1-xZr_xO₂ FeFET Synapses

Analog in-memory computing can accelerate edge-AI inference by executing vector-matrix multiplication directly in memory crossbars, but practical analog deployment is constrained by finite weight resolution and stochastic programming. Here we demonstrate program-pulse-engineered MoS_2-Hf_1-xZr_xO₂ (HZO) ferroelectric field-effect transistor (FeFET) synapses and a hardware-consistent quantized machine-learning workflow for noise-robust analog inference. The device integrates an atomically thin monolayer MoS₂ channel, representing ultimate body-thickness scaling in advanced logic roadmaps, with a CMOS-compatible HZO ferroelectric gate stack. Operating in a near-coercive regime, trains of identical potentiation/depression pulses yield gradual and reversible multi-level conductance updates with ∼100 states, enabling array-realistic programming without per-device program-and-verify. Systematic pulse engineering provides knobs to tune update granularity and dynamic range, and enables offset control of the usable conductance window via asymmetric depression conditions. Crucially, we quantify cycle-to-cycle write variability using state-dependent ΔG statistics and incorporate the measured quantization levels and noise directly into training and evaluation. Using MNIST as a benchmark, noise-aware quantization-aware training outperforms post-training quantization across quantization levels and noise scaling, sustaining up to ∼97% test accuracy under low precision and elevated noise. These results connect measured programming physics to robust quantized analog inference and establish practical device-algorithm co-design principles for scalable FeFET-based synaptic hardware.