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Stefan Scholze

Showing results (1-10 of 6) with videos related to

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IEEE Transactions on Biomedical Circuits and Systems|February 14, 2015
A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor CircuitsChristian Mayr, Johannes Partzsch, Marko Noack, et al.
Frontiers in Neuroscience|February 21, 2015
Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOSMarko Noack, Johannes Partzsch, Christian G Mayr, et al.
Frontiers in Neuroscience|October 22, 2011
VLSI Implementation of a 2.8 Gevent/s Packet-Based AER Interface with Routing and Event Sorting FunctionalityStefan Scholze, Stefan Schiefer, Johannes Partzsch, et al.
IEEE Transactions on Biomedical Circuits and Systems|January 13, 2022
A 16-Channel Fully Configurable Neural SoC With 1.52 μW/Ch Signal Acquisition, 2.79 μW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOISeyed Mohammad Ali Zeinolabedin, Franz Marcus Schuffny, Richard George, et al.
Frontiers in Neuroscience|November 8, 2024
68-channel neural signal processing system-on-chip with integrated feature extraction, compression, and hardware accelerators for neuroprosthetics in 22 nm FDSOILiyuan Guo, Annika Weiße, Seyed Mohammad Ali Zeinolabedin, et al.
Biological Cybernetics|May 28, 2011
A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systemsDaniel Brüderle, Mihai A Petrovici, Bernhard Vogginger, et al.
Pageof 1

Showing results (1-10 of 6) with videos related to

Sort By:
Pageof 1
IEEE Transactions on Biomedical Circuits and Systems|February 14, 2015
A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor CircuitsChristian Mayr, Johannes Partzsch, Marko Noack, et al.
Frontiers in Neuroscience|February 21, 2015
Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOSMarko Noack, Johannes Partzsch, Christian G Mayr, et al.
Frontiers in Neuroscience|October 22, 2011
VLSI Implementation of a 2.8 Gevent/s Packet-Based AER Interface with Routing and Event Sorting FunctionalityStefan Scholze, Stefan Schiefer, Johannes Partzsch, et al.
IEEE Transactions on Biomedical Circuits and Systems|January 13, 2022
A 16-Channel Fully Configurable Neural SoC With 1.52 μW/Ch Signal Acquisition, 2.79 μW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOISeyed Mohammad Ali Zeinolabedin, Franz Marcus Schuffny, Richard George, et al.
Frontiers in Neuroscience|November 8, 2024
68-channel neural signal processing system-on-chip with integrated feature extraction, compression, and hardware accelerators for neuroprosthetics in 22 nm FDSOILiyuan Guo, Annika Weiße, Seyed Mohammad Ali Zeinolabedin, et al.
Biological Cybernetics|May 28, 2011
A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systemsDaniel Brüderle, Mihai A Petrovici, Bernhard Vogginger, et al.
Pageof 1