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Tomonori Nishimura

Showing results (1-10 of 21) with videos related to

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Nature Communications|December 15, 2015
Positive-bias gate-controlled metal-insulator transition in ultrathin VO2 channels with TiO2 gate dielectricsTakeaki Yajima, Tomonori Nishimura, Akira Toriumi
Small (Weinheim an Der Bergstrasse, Germany)|January 17, 2017
Identifying the Collective Length in VO<sub>2</sub> Metal-Insulator TransitionsTakeaki Yajima, Tomonori Nishimura, Akira Toriumi
ACS Applied Materials & Interfaces|September 3, 2021
Thermodynamic Perspective on the Oxidation of Layered Materials and Surface Oxide Amelioration in 2D DevicesYih-Ren Chang, Tomonori Nishimura, Kosuke Nagashio
Small (Weinheim an Der Bergstrasse, Germany)|January 11, 2023
A Monolayer MoS<sub>2</sub> FET with an EOT of 1.1 nm Achieved by the Direct Formation of a High-κ Er<sub>2</sub> O<sub>3</sub> Insulator Through Thermal EvaporationHaruki Uchiyama, Kohei Maruyama, Edward Chen, et al.
Nanoscale Advances|February 9, 2023
Experimental verification of SO<sub>2</sub> and S desorption contributing to defect formation in MoS<sub>2</sub> by thermal desorption spectroscopyShuhong Li, Tomonori Nishimura, Mina Maruyama, et al.
ACS Applied Materials & Interfaces|May 27, 2022
Current Injection into Single-Crystalline Carbon-Doped <i>h</i>-BN toward Electronic and Optoelectronic ApplicationsSupawan Ngamprapawat, Tomonori Nishimura, Kenji Watanabe, et al.
ACS Applied Materials & Interfaces|April 20, 2022
Performance Enhancement of SnS/<i>h</i>-BN Heterostructure p-Type FET via the Thermodynamically Predicted Surface Oxide Conversion MethodYih-Ren Chang, Tomonori Nishimura, Takashi Taniguchi, et al.
ACS Nano|March 25, 2021
Material and Device Structure Designs for 2D Memory Devices Based on the Floating Gate Voltage TrajectoryTaro Sasaki, Keiji Ueno, Takashi Taniguchi, et al.
Small (Weinheim an Der Bergstrasse, Germany)|November 3, 2020
Understanding the Memory Window Overestimation of 2D Materials Based Floating Gate Type Memory Devices by Measuring Floating Gate VoltageTaro Sasaki, Keiji Ueno, Takashi Taniguchi, et al.
ACS Applied Materials & Interfaces|May 23, 2022
Ultrafast Operation of 2D Heterostructured Nonvolatile Memory Devices Provided by the Strong Short-Time Dielectric Breakdown Strength of <i>h</i>-BNTaro Sasaki, Keiji Ueno, Takashi Taniguchi, et al.
Pageof 3

Showing results (1-10 of 21) with videos related to

Sort By:
Pageof 3
Nature Communications|December 15, 2015
Positive-bias gate-controlled metal-insulator transition in ultrathin VO2 channels with TiO2 gate dielectricsTakeaki Yajima, Tomonori Nishimura, Akira Toriumi
Small (Weinheim an Der Bergstrasse, Germany)|January 17, 2017
Identifying the Collective Length in VO<sub>2</sub> Metal-Insulator TransitionsTakeaki Yajima, Tomonori Nishimura, Akira Toriumi
ACS Applied Materials & Interfaces|September 3, 2021
Thermodynamic Perspective on the Oxidation of Layered Materials and Surface Oxide Amelioration in 2D DevicesYih-Ren Chang, Tomonori Nishimura, Kosuke Nagashio
Small (Weinheim an Der Bergstrasse, Germany)|January 11, 2023
A Monolayer MoS<sub>2</sub> FET with an EOT of 1.1 nm Achieved by the Direct Formation of a High-κ Er<sub>2</sub> O<sub>3</sub> Insulator Through Thermal EvaporationHaruki Uchiyama, Kohei Maruyama, Edward Chen, et al.
Nanoscale Advances|February 9, 2023
Experimental verification of SO<sub>2</sub> and S desorption contributing to defect formation in MoS<sub>2</sub> by thermal desorption spectroscopyShuhong Li, Tomonori Nishimura, Mina Maruyama, et al.
ACS Applied Materials & Interfaces|May 27, 2022
Current Injection into Single-Crystalline Carbon-Doped <i>h</i>-BN toward Electronic and Optoelectronic ApplicationsSupawan Ngamprapawat, Tomonori Nishimura, Kenji Watanabe, et al.
ACS Applied Materials & Interfaces|April 20, 2022
Performance Enhancement of SnS/<i>h</i>-BN Heterostructure p-Type FET via the Thermodynamically Predicted Surface Oxide Conversion MethodYih-Ren Chang, Tomonori Nishimura, Takashi Taniguchi, et al.
ACS Nano|March 25, 2021
Material and Device Structure Designs for 2D Memory Devices Based on the Floating Gate Voltage TrajectoryTaro Sasaki, Keiji Ueno, Takashi Taniguchi, et al.
Small (Weinheim an Der Bergstrasse, Germany)|November 3, 2020
Understanding the Memory Window Overestimation of 2D Materials Based Floating Gate Type Memory Devices by Measuring Floating Gate VoltageTaro Sasaki, Keiji Ueno, Takashi Taniguchi, et al.
ACS Applied Materials & Interfaces|May 23, 2022
Ultrafast Operation of 2D Heterostructured Nonvolatile Memory Devices Provided by the Strong Short-Time Dielectric Breakdown Strength of <i>h</i>-BNTaro Sasaki, Keiji Ueno, Takashi Taniguchi, et al.
Pageof 3