Kaustav Banerjee
10PUBLICATIONS
7CO-AUTHORS
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Publications (10)
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|Jul 07, 2025
CMOS-Compatible Pressure-Assisted Solid-Phase-Diffusion Technique for Large-Area Multilayer Graphene Synthesis.Kunjesh Agashiwala, Ankit Kumar, Lin Xu
|Apr 22, 2024
An ultra energy-efficient hardware platform for neuromorphic computing enabled by 2D-TMD tunnel-FETs.Arnab Pal, Zichun Chai, Junkai Jiang
|Apr 25, 2022
Quantum-Engineered Devices Based on 2D Materials for Next-Generation Information Processing and Storage.Arnab Pal, Shuo Zhang, Tanmay Chavan
|Jun 12, 2021
Defect and strain engineering of monolayer WSe2 enables site-controlled single-photon emission up to 150 K.Kamyar Parto, Shaimaa I Azzam, Kaustav Banerjee
|Feb 26, 2020
Author Correction: Is negative capacitance FET a steep-slope logic switch?Wei Cao, Kaustav Banerjee
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