Tudor Mocioi

1PUBLICATIONS
4CO-AUTHORS
Digital processor architectures
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Publications (1)

|Sep 30, 2026
Hardware Acceleration of Stochastic Neural Networks Enabled by Bit-Cell Level Co-Design of Magnetic Tunnel Junctions.

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Frequent Collaborators

1 joint publications

Qiuyuan Wang

1 joint publications

Dooyong Koh

1 joint publications

Yabin Fan

1 joint publications

Marc Baldo