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相关概念视频

Biasing of FET01:22

Biasing of FET

300
Biasing a Junction Field Effect Transistor (JFET) is crucial for setting operational parameters and ensuring efficient functioning in electronic circuits. JFETs are characterized by using a single carrier type in N-channel or P-channel configurations, where the channel is surrounded by PN junctions. These junctions are central to the device's ability to control current flow.
In an N-channel JFET, the structure consists of N-type material forming the channel on a P-type substrate, with the...
300
Field Effect Transistor01:29

Field Effect Transistor

439
Field-effect transistors (FETs) are integral to electronic circuits and distinguished by their three-terminal setup: the gate, drain, and source. These transistors operate as unipolar devices, which utilize either electrons or holes as charge carriers, in contrast to bipolar transistors, which use both types of carriers. The primary function of the FET is to modulate the flow of these carriers from the source to the drain through a channel. The voltage difference between the gate and source...
439
MOS Capacitor01:25

MOS Capacitor

815
A Metal-Oxide-Semiconductor (MOS) capacitor is a fundamental structure used extensively in semiconductor device technology, particularly in the fabrication of integrated circuits and MOSFETs (metal-oxide-semiconductor field-effect transistors). The MOS capacitor consists of three layers: a metal gate, a dielectric oxide, and a semiconductor substrate.
The metal gate is typically made from highly conductive materials such as aluminum or polysilicon. Beneath the metal gate lies a thin layer of...
815
MOSFET: Enhancement Mode01:22

MOSFET: Enhancement Mode

363
Enhancement-mode MOSFETs are pivotal components in electronics, distinguished by their capacity to act as highly efficient switches. They are part of the larger family of metal-oxide Semiconductor Field-Effect Transistors (MOSFETs). They are available in two types: p-channel and n-channel, each tailored to specific polarity operations.
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no...
363
Design Example: Capacitance Multiplier Circuit01:20

Design Example: Capacitance Multiplier Circuit

794
In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.
794
Metal-Semiconductor Junctions01:24

Metal-Semiconductor Junctions

360
The contact of metal and semiconductor can lead to the formation of a junction with either Schottky or Ohmic behavior.
Schottky Barriers
Schottky barriers arise when a metal with a work function (Φm) contacts a semiconductor with a different work function (Φs). Initially, electrons transfer until the Fermi levels of the metal and semiconductor align at equilibrium. For instance, if Φm > Φs, the semiconductor Fermi level is higher than the metal's before contact. The...
360

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In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx
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使用多层次的Cell FeFET进行内存计算交叉杆的首次演示.

Taha Soliman1, Swetaki Chatterjee2,3, Nellie Laleni4

  • 1Robert Bosch GmbH, Renningen, Germany. taha.soliman@de.bosch.com.

Nature communications
|October 10, 2023
PubMed
概括

本研究介绍了一种新的内存计算 (IMC) 交叉杆宏,使用多级铁电场效应晶体管 (FeFET) 细胞进行高效的多位倍增和积累 (MAC) 操作,实现高精度和性能.

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科学领域:

  • 半导体设备物理学 半导体设备物理
  • 人工智能硬件是人工智能的硬件.
  • 计算机架构 计算机架构

背景情况:

  • 人工智能 (AI) 的进步需要高效的计算和内存解决方案.
  • 内存计算 (IMC) 架构为应对这些挑战提供了一个有前途的方法.
  • 铁电场效应晶体管 (FeFET) 正在成为高级内存和计算的关键组件.

研究的目的:

  • 引入一个新的IMC横杆宏,采用多层FeFET单元.
  • 为了使多位的乘法和积累 (MAC) 操作使用单个FeFET每电阻 (1FeFET-1R) 单元.
  • 为了最大限度地减少设备变化对IMC计算准确性的影响.

主要方法:

  • 使用28nmHKMG技术的FeFET设备设计和制造1FeFET-1R横杆宏.
  • 在MAC操作中利用FeFET中存储数据的电气特性.
  • 编码MAC导致激活时间和累积电流,绕过传统的电阻式内存方法.

主要成果:

  • 实验验证显示高精度的手写识别 (96.6%) 和图像分类 (91.5%) 没有再培训.
  • 实现了885.4 TOPS/W的特殊能源效率,几乎是现有设计的两倍.
  • 使用多态FeFET单元格成功实现了完整的MAC操作宏,保持了交叉杆密度.

结论:

  • 拟议的基于FeFET的IMC宏为高性能,低功耗AI硬件提供了可行的解决方案.
  • 这项工作代表了实现密集,高效的内存计算架构的重大进步.
  • 这种新的方法展示了未来人工智能加速器的多层FeFET细胞的潜力.