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VLSI architectures for computing multiplications and inverses in GF(2m).
C C Wang1, T K Truong, H M Shao
1Jet Propulsion Laboratory, California Institute of Technology, Pasadena 91109, USA.
IEEE Transactions on Computers. Institute of Electrical and Electronics Engineers
|August 1, 1985
Summary
This study introduces a pipeline architecture for efficient multiplication and inversion in Galois fields (GF(2m)) using the Massey-Omura algorithm. The design is optimized for VLSI implementation, enhancing Reed-Solomon coders and cryptography.
Area of Science:
- Digital arithmetic logic
- Galois field theory
- VLSI design
Background:
- Finite field arithmetic is crucial for Reed-Solomon codes and cryptography.
- Efficient multiplication and inversion algorithms are needed for VLSI implementation.
- The Massey-Omura algorithm offers a new approach for Galois field multiplication.
Purpose of the Study:
- To develop a pipeline structure for the Massey-Omura multiplier in GF(2m).
- To design a pipeline architecture for computing inverse elements in GF(2m) using normal basis properties.
- To create VLSI-suitable designs for finite field arithmetic.
Main Methods:
- Implementation of the Massey-Omura multiplier using a pipeline structure.
- Leveraging the squaring property of normal basis representation.
- Development of a pipeline architecture for inverse element computation.
Main Results:
- A regular, simple, and expandable pipeline architecture for the Massey-Omura multiplier.
- An efficient pipeline architecture for computing inverse elements in GF(2m).
- Designs are well-suited for VLSI implementation.
Conclusions:
- The proposed pipeline architectures for Massey-Omura multiplication and inverse computation are efficient.
- The designs are regular, simple, and expandable, making them ideal for VLSI.
- This work advances the implementation of finite field arithmetic for coding and cryptography.