A VLSI design of a pipeline Reed-Solomon decoder.

Area of Science:

• Coding Theory
• Digital Signal Processing
• VLSI Design

Background:

• Reed-Solomon (RS) codes are widely used for error correction in digital communication and data storage systems.
• Efficient decoding algorithms are crucial for high-speed implementations, particularly in Very Large Scale Integration (VLSI) circuits.
• Existing decoding methods often involve complex computations, including the inversion of field elements, which can be computationally intensive and challenging for hardware implementation.

Purpose of the Study:

• To develop a novel pipeline decoder architecture for Reed-Solomon (RS) codes.
• To design a decoder structure that is regular, simple, and suitable for efficient VLSI implementation.
• To introduce a modified Euclidean algorithm that avoids the computation of inverse field elements during error-locator polynomial calculation.

Main Methods:

• A pipeline decoder structure, analogous to a systolic array, was designed for RS code decoding.
• A modified Euclidean algorithm was developed to compute the error-locator polynomial.
• The modified algorithm specifically eliminates the need for inverse field element computations.

Main Results:

• The proposed decoder architecture exhibits a regular and simple structure, well-suited for VLSI implementation.
• The modified Euclidean algorithm successfully computes the error-locator polynomial without requiring inverse field elements.
• An illustrative example demonstrates the pipeline and systolic array characteristics of the decoder for a specific RS code.

Conclusions:

• The developed pipeline decoder offers an efficient and hardware-friendly approach for Reed-Solomon (RS) code decoding.
• The elimination of inverse field element computations in the modified Euclidean algorithm simplifies the decoder's hardware complexity.
• The proposed architecture holds significant potential for practical applications requiring high-performance error correction.