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Holographic voltage profiling on 75 nm gate architecture CMOS devices
Alexander E Thesen1, Bernhard G Frost, David C Joy
1Department of Physics, 401 Nielson Physics Bldg., University of Tennessee, Knoxville 37996, USA. athesen@utk.edu
Ultramicroscopy
|January 14, 2003
Abstract:
Voltage profiles of the source-drain region of a CMOS transistor with 75nm gate architecture taken from an off-the-shelf Intel PIII processor are presented. The sample preparation using a dual beam system is discussed as well as details of the electron optical setup of the microscope. Special attention is given to the analysis of the reconstructed holograms.