Generalized disjunction decomposition for evolvable hardware

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Hardware Design

Background:

• Evolvable hardware (EHW) utilizes evolutionary algorithms (EA) for self-reconfiguring hardware design.
• Scalability remains a significant challenge, limiting the complexity of circuits that can be evolved.
• Existing EHW methods struggle with large-scale circuit evolution.

Purpose of the Study:

• Introduce a novel decomposition strategy, generalized disjunction decomposition (GDD), to address EHW scalability limitations.
• Enable the evolution of larger and more complex digital logic circuits.
• Provide a comprehensive overview of EHW systems and their applications.

Main Methods:

• Developed and implemented the generalized disjunction decomposition (GDD) strategy for EHW.
• Tested GDD on benchmark circuits (multipliers, parity, MCNC library) and random circuits.
• Employed an extrinsic EHW system with a (1 + lambda) evolution strategy, running each circuit evolution 100 times for statistical relevance.

Main Results:

• GDD significantly improves the evolution of logic circuits, reducing the number of generations required.
• The method reduces computational time by decreasing the time per EA iteration.
• GDD successfully enabled the evolution of larger circuits than previously possible in EHW.

Conclusions:

• Generalized disjunction decomposition is an effective strategy for enhancing the scalability of evolvable hardware.
• The proposed method offers significant improvements in efficiency and circuit size for EHW applications.
• GDD represents a breakthrough in evolving complex digital circuits using evolutionary algorithms.