Real-time reconfigurable linear threshold elements implemented in floating-gate CMOS

Area of Science:

• Microelectronic Engineering
• Solid-State Circuits
• Low-Power Electronics

Background:

• Traditional digital circuits face limitations in power consumption and reconfigurability.
• Floating-gate technology offers non-volatile memory and programmability advantages.
• Developing efficient linear threshold elements is crucial for advanced computing architectures.

Purpose of the Study:

• To introduce a new class of real-time reconfigurable UV-programmable floating-gate (FGUVMOS) linear threshold elements.
• To propose a novel design methodology for creating larger and more efficient FGUVMOS circuitry.
• To explore the potential of these elements as fundamental building blocks for neural networks.

Main Methods:

• Theoretical analysis and computer simulations.
• Laboratory measurements on fabricated integrated circuits.
• Development of a design method utilizing basic two-MOSFET circuits extensively.

Main Results:

• Demonstrated FGUVMOS linear threshold elements operating in the pA to μA current range.
• Achieved ultra-low-power operation with supply voltages as low as 93 mV.
• Successfully implemented basic digital functions (CARRY, NOR, NAND, INVERT) using 2-MOSFET circuits.

Conclusions:

• The proposed FGUVMOS elements offer significant ultra-low-power potential.
• The new design method facilitates the creation of larger, more compact, and easily testable FGUVMOS circuitry.
• These elements are promising candidates for building blocks in neural network applications.