An ART1 microchip and its use in multi-ART1 systems

Area of Science:

• Artificial Intelligence
• Neuromorphic Engineering
• VLSI Design

Background:

• Previous ART1 architecture chips suffered from large silicon area (1 cm²) and low yield (6%).
• Area-intensive circuit elements, like precise current source arrays, were key limitations.

Purpose of the Study:

• To develop an improved ART1 chip prototype with reduced area and higher yield.
• To maintain or improve precision and speed compared to prior designs.
• To enhance robustness for multichip system integration.

Main Methods:

• Implemented area-consuming circuit elements using a novel approach based on transistor mismatch characterization (ES2-1.0 µm CMOS).
• Fabricated a new prototype capable of clustering 50-bit input patterns into ten categories.
• Evaluated performance metrics including area, yield, precision, and speed.

Main Results:

• The new prototype chip occupies 15 times less area than the previous version.
• Achieved a significantly improved yield performance of 98%.
• Maintained the same precision and speed as the earlier, larger chip.

Conclusions:

• The improved ART1 chip offers a more efficient and robust solution for real-time clustering.
• The design facilitates the easy assembly of multichip ART1 and ARTMAP systems.
• This work demonstrates the feasibility of a two-chip ART1 system and a three-chip ARTMAP system.