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Two-dimensional spatio-temporal dynamics of analog image processing neural networks.
H Kobayashi1, T Matsumoto, J Sanekata
1Teratec Corp., Tokyo.
IEEE Transactions on Neural Networks
|January 1, 1995
Summary
This study addresses temporal and spatial dynamics in analog image-processing neural networks using CMOS LSI. It provides formulas to ensure chip stability and predictable voltage distribution for reliable image processing.
Area of Science:
- Electrical Engineering
- Computer Science
- Artificial Intelligence
Background:
- Analog image-processing neural networks utilize 2D arrays of processing elements.
- Implementation with CMOS LSI introduces temporal and spatial dynamics challenges.
- Temporal instability and unpredictable voltage distribution hinder image processing.
Purpose of the Study:
- To analyze and derive explicit formulas for the 2D dynamics in analog image-processing neural networks.
- To provide design and analysis tools for stable and predictable network behavior.
- To ensure the usability of CMOS LSI-based image-processing chips.
Main Methods:
- Analysis of temporal dynamics induced by parasitic capacitors in MOS transistors.
- Investigation of spatial dynamics arising from node voltage distribution in the array structure.
- Derivation of explicit mathematical formulas and relationships for 2D dynamics.
Main Results:
- Formulas characterizing temporal dynamics, crucial for chip stability.
- Relationships defining spatial dynamics, essential for controlled voltage distribution.
- Identification of design parameters to mitigate undesirable dynamic behaviors.
Conclusions:
- The derived formulas are vital for designing stable and predictable analog image-processing neural networks.
- Understanding and controlling 2D dynamics ensures reliable image processing with CMOS LSI.
- This work offers foundational analysis for developing robust analog neural network hardware.