VLSI implementation of synaptic weighting and summing in pulse coded neural-type cells

Area of Science:

• Neuroscience
• Electrical Engineering
• Computer Science

Background:

• Traditional computing faces limitations in energy efficiency and speed for complex tasks.
• Neuromorphic computing offers a promising alternative by mimicking biological neural structures.
• Efficient hardware implementation of synaptic functions is crucial for advancing neuromorphic systems.

Purpose of the Study:

• To present a novel hardware realization for synaptic weighting and summing.
• To introduce a pulse duty cycle modulation technique for information encoding in neural-type cells (NTCs).
• To demonstrate the feasibility of the proposed approach through integrated circuit design and measurements.

Main Methods:

• Utilizing pulse-coded neural-type cells (NTCs) as the basic information processing element.
• Employing voltage-controlled resistors for encoding information into pulse duty cycles.
• Implementing summation through a simple capacitor circuit acting as a current integrator.
• Fabricating and measuring an integrated circuit design.

Main Results:

• Successful hardware realization of synaptic weighting and summing functionalities.
• Demonstration of information encoding using pulse duty cycles.
• Validation of the capacitor circuit as an effective current integrator for summation.
• Experimental measurements confirming the performance of the fabricated integrated design.

Conclusions:

• The proposed hardware realization effectively implements synaptic weighting and summing using pulse-coded NTCs.
• The pulse duty cycle modulation technique provides a viable method for information encoding in neuromorphic hardware.
• The integrated design demonstrates the practical applicability of the developed approach for neuromorphic computing circuits.