Complementary symmetry nanowire logic circuits: experimental demonstrations and in silico optimizations

Area of Science:

• Nanotechnology
• Electronics Engineering
• Materials Science

Background:

• Complementary symmetry (CS) Boolean logic offers energy efficiency by preventing direct power-to-ground pathways.
• Implementing CS logic with nanowires is challenging due to gate complexity and signal restoration requirements.

Purpose of the Study:

• To investigate the feasibility of constructing complementary symmetry (CS) logic circuits using silicon nanowires.
• To address the challenges of implementing CS logic, including signal restoration, high gain, and noise margins.

Main Methods:

• Fabrication of CS logic circuits using 16 nm wide silicon nanowire arrays.
• Development of in silico models for CS inverters utilizing experimentally derived FET properties.
• Experimental characterization of fabricated CS inverters and logic gates.

Main Results:

• Demonstration of CS logic gates, including an XOR gate, with signal restoration and the ability to drive other gates.
• Achieved CS inverters with a gain approaching 50 and robust noise margins through in silico modeling feedback.
• Observed significant device-to-device fluctuations in single nanowire-based logic gates.

Conclusions:

• Silicon nanowire-based CS logic circuits are a viable approach for energy-efficient, large-scale logic implementation.
• In silico modeling is crucial for optimizing device fabrication and achieving high-performance CS logic.
• Further research is needed to mitigate device-to-device variations in single nanowire logic gates.