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Related Experiment Video

Updated: Jun 11, 2026

Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon
06:57

Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon

Published on: July 17, 2020

Vertically oriented epitaxial germanium nanowires on silicon substrates using thin germanium buffer layers.

Jae Hun Jung1, Hyun Sik Yoon, Yu Lee Kim

  • 1Department of Physics, Dong-A University, Hadan-2-dong, Sahagu, Busan 604-714, Korea.

Nanotechnology
|June 30, 2010
PubMed
Summary

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Researchers developed a method for growing vertically oriented Germanium (Ge) nanowires on Silicon (Si) substrates. This technique utilizes a thin Germanium buffer layer, achieving a high yield of 96.3% for vertically aligned Ge nanowires suitable for microelectronics.

Area of Science:

  • Materials Science
  • Nanotechnology
  • Semiconductor Physics

Background:

  • Vertically oriented Germanium (Ge) nanowires are crucial for advanced semiconductor devices.
  • Direct growth of Ge nanowires on Silicon (Si) is hindered by Si oxidation during Au nanoparticle seeding.
  • Existing methods face challenges in achieving high yields of vertically aligned Ge nanowires.

Purpose of the Study:

  • To develop a robust method for fabricating vertically oriented Ge nanowires on Si(111) substrates.
  • To overcome the Si oxidation issue during the vapor-liquid-solid growth of Ge nanowires.
  • To achieve high yield and enable further functionalization, such as branched nanowire growth.

Main Methods:

  • Chemical vapor deposition (CVD) with Au nanoparticles for Ge nanowire growth.

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Last Updated: Jun 11, 2026

Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon
06:57

Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon

Published on: July 17, 2020

Analysis of Contact Interfaces for Single GaN Nanowire Devices
11:13

Analysis of Contact Interfaces for Single GaN Nanowire Devices

Published on: November 15, 2013

Developing High Performance GaP/Si Heterojunction Solar Cells
10:31

Developing High Performance GaP/Si Heterojunction Solar Cells

Published on: November 16, 2018

  • Introduction of a thin Ge buffer layer grown at low temperatures (<600°C) prior to nanowire seeding.
  • Secondary seeding technique for growing branched Ge nanowires.

    • Main Results:

    • Successfully realized vertically oriented Ge nanowires on Si(111) with a yield of 96.3%.
    • The thin Ge buffer layer effectively suppressed Si oxidation, enabling high-yield vertical growth.
    • Demonstrated the capability to grow branched Ge nanowires on the vertically oriented structures.

    Conclusions:

    • The developed low-temperature Ge buffer layer method provides a high-yield pathway for vertically oriented Ge nanowires on Si.
    • This technique is compatible with Si-based microelectronics fabrication due to its moderate processing conditions.
    • The method opens possibilities for complex nanowire architectures and integration into next-generation electronic devices.