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Scaling constraints in nanoelectronic random-access memories.
Christian J Amsinck1, Neil H Di Spigna, David P Nackashi
1North Carolina State University, PO Box 7911, Raleigh, NC 27695-7911, USA.
Nanotechnology
|September 7, 2010
Summary
Nanoelectronic memory systems, like molecular and magnetic tunnel junction (MTJ) MRAM, offer area advantages. Their scalability depends on the device
Area of Science:
- Nanoelectronics
- Molecular electronics
- Non-volatile memory technologies
Background:
- Nanoelectronic molecular and magnetic tunnel junction (MTJ) MRAM crossbar memory systems offer significant area advantages over CMOS systems.
- The scalability of these conductivity-switched RAM arrays is crucial for future high-density memory applications.
Purpose of the Study:
- To examine the scalability of nanoelectronic memory arrays.
- To establish criteria for correct functionality based on readout margin.
- To quantify the impact of device and interconnect architecture on scalability.
Main Methods:
- Combined circuit theoretical modeling and simulation approach.
- Analysis of device and interconnect architecture effects.
- Quantification of scalability criteria.
Main Results:
- A minimum on/off ratio of 7 is required for a 64x64 array with a 10% readout margin.
- An on/off ratio of 43 is necessary to scale the memory to a 512x512 array.
- Criteria for large-scale integration of molecular devices were established.
Conclusions:
- The study provides essential criteria for the large-scale integration of molecular memory devices.
- Device on/off ratio is a critical factor determining the scalability of nanoelectronic memory arrays.
- Findings guide future molecular device design for advanced memory systems.
