Sub-30 nm gate template fabrication for nanoimprint lithography using spacer patterning technology

Area of Science:

• Materials Science
• Electrical Engineering
• Nanotechnology

Background:

• Fabrication of nano-scale Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) requires precise control over gate dimensions.
• Current photolithography techniques face limitations in achieving sub-30 nm feature sizes.
• Development of advanced patterning technologies is crucial for next-generation semiconductor devices.

Purpose of the Study:

• To present a novel spacer patterning technology for fabricating sub-30 nm gate templates.
• To demonstrate the capability of achieving critical dimensions smaller than conventional optical lithography.
• To enable the production of large-area templates for nano-scale MOSFETs.

Main Methods:

• Development of a spacer patterning technology utilizing a poly-silicon micro-feature.
• Application of chemical vapor deposition (CVD) for SiO2 spacer formation.
• Utilizing conventional dry etching and chemical mechanical polishing for structure definition.

Main Results:

• Successfully demonstrated sub-30 nm structures using the developed spacer patterning technology.
• The minimum feature size was determined by the CVD film thickness, not photolithography.
• Achieved a large-area template with critical dimensions significantly smaller than those from optical lithography.

Conclusions:

• The presented spacer patterning technology offers a viable method for creating sub-30 nm gate templates.
• This approach overcomes the resolution limits of optical lithography for nano-scale MOSFET fabrication.
• The technology holds promise for advancing the manufacturing of high-performance nano-scale semiconductor devices.