A 124 Mpixels/s VLSI design for histogram-based joint bilateral filtering.

Area of Science:

• Computer Engineering
• Image Processing
• Hardware Acceleration

Background:

• Bilateral Filtering (BF) and Joint Bilateral Filtering (JBF) are computationally intensive image processing techniques.
• High memory cost, computational complexity, and bandwidth requirements limit the practical application of BF and JBF.
• Existing methods struggle with large range tables and inefficient memory usage.

Purpose of the Study:

• To propose an efficient and scalable hardware design for histogram-based BF and JBF.
• To address the challenges of high memory cost, computational complexity, and bandwidth.
• To optimize range table size and access for improved performance.

Main Methods:

• Implemented memory reduction techniques exploiting progressive computing characteristics.
• Utilized architecture design techniques including range domain parallelism.
• Leveraged computing order and numerical properties for optimization.

Main Results:

• Achieved a memory cost reduction to 0.003%-0.020% compared to original approaches.
• Successfully addressed complexity, bandwidth, and range-table issues.
• An example design achieved 124 Mpixels/s throughput with 356-K gate counts and 23-KB on-chip memory.

Conclusions:

• The proposed design offers significant improvements in efficiency and scalability for BF and JBF.
• The memory reduction and architecture design techniques provide a practical solution for hardware implementation.
• This work enables high-throughput image filtering with reduced hardware resources.