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Updated: May 31, 2026

Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices
Published on: December 7, 2017
Oxide-confined formation of germanium nanowire heterostructures for high-performance transistors
Jianshi Tang1, Chiu-Yen Wang, Faxian Xiu
1Device Research Laboratory, Department of Electrical Engineering, University of California, Los Angeles, California 90095, USA.
Abstract:
Over the past several years, the formation of nanowire heterostructures via a solid-state reaction between a semiconductor nanowire and metal contact pads has attracted great interest. This is owing to its ready application in nanowire field-effect transistors (FETs) with a well-controlled channel length using a facile rapid thermal annealing process. We report the effect of oxide confinement on the formation of Ge nanowire heterostructures via a controlled reaction between a vapor-liquid-solid-grown, single-crystalline Ge nanowire and Ni pads. In contrast to the previous formation of Ni(2)Ge/Ge/Ni(2)Ge nanowire heterostructures, a segment of high-quality epitaxial NiGe was formed between Ni(2)Ge and Ge with the confinement of Al(2)O(3) during annealing. Significantly, back-gate FETs based on this Ni(2)Ge/NiGe/Ge/NiGe/Ni(2)Ge heterostructure demonstrated a high-performance p-type transistor behavior, showing a large on/off ratio of more than 10(5) and a high normalized transconductance of 2.4 μS/μm. The field-effect hole mobility was extracted to be 210 cm(2)/(V s). Temperature-dependent I-V measurements further confirmed that NiGe has an ideal ohmic contact to p-type Ge with a small Schottky barrier height of 0.11 eV. Moreover, the hysteresis during gate bias sweeping was significantly reduced after Al(2)O(3) passivation, and our Ω-gate Ge nanowire FETs using Al(2)O(3) as the top-gate dielectric showed an enhanced subthreshold swing and transconductance. Therefore, we conclude that the Al(2)O(3) layer can effectively passivate the Ge surface and also serve as a good gate dielectric in Ge top-gate FETs. Our innovative approach provides another freedom to control the growth of nanowire heterostructure and to further achieve high-performance nanowire transistors.
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