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Defect tolerance in resistor-logic demultiplexers for nanoelectronics
Philip J Kuekes1, Warren Robinett, R Stanley Williams
1Quantum Science Research, Hewlett Packard Labs, 1501 Page Mill Road, Palo Alto, CA 94304, USA.
Nanotechnology
|July 6, 2011
Summary
Resistor-logic demultiplexers show defect tolerance in nanocircuitry. The design uses coding and avoidance layers to maintain performance, even with multiple nanowire defects.
Area of Science:
- Electrical Engineering
- Nanotechnology
- Computer Science
Background:
- Nanocircuitry is prone to high defect rates.
- Resistor-logic demultiplexers are a key component in nanoscale systems.
- Understanding defect impact is crucial for reliable nanocircuit design.
Purpose of the Study:
- To analyze the performance of resistor-logic demultiplexers under various defect conditions.
- To evaluate the defect tolerance capabilities of these circuits.
- To identify strategies for achieving reliable operation in the presence of defects.
Main Methods:
- Simulated defect scenarios including stuck-open, stuck-closed, stuck-short, broken-wire, and adjacent-wire-short defects.
- Analyzed voltage distributions on nanowire output lines.
- Investigated the impact of defect types and quantities on demultiplexer functionality.
Main Results:
- Resistor-logic demultiplexers tolerate limited stuck-closed, stuck-open, and broken-wire defects, with minor voltage margin degradation.
- Error-free performance is achievable with stuck-short and adjacent-wire-short defects by reducing the number of usable output lines.
- The circuit exhibits two layers of defect tolerance: coding for yield and avoidance for error-free operation.
Conclusions:
- The proposed resistor-logic demultiplexer design demonstrates significant defect tolerance.
- The dual-layer approach (coding and avoidance) enhances the robustness and reliability of nanocircuitry.
- This design offers a pathway to practical implementation of nanocircuitry despite fabrication challenges.
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