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Design, Surface Treatment, Cellular Plating, and Culturing of Modular Neuronal Networks Composed of Functionally Inter-connected Circuits
Published on: April 15, 2015
Massively parallel neural signal processing: System-on-Chip design with FPGAs.
Karthikeyan Balasubramanian1, Iyad Obeid
1Neural Instrumentation Lab, Temple University, Philadelphia, PA 19122, USA.bkintex@temple.edu
Summary
This study presents a scalable System-on-Chip (SoC) architecture for parallel neural signal processing, featuring a reconfigurable platform with real-time spike detection for extensive neural recordings.
Area of Science:
- Neuroscience
- Computer Engineering
- Signal Processing
Background:
- Neural recordings generate massive datasets requiring efficient processing.
- Existing systems often lack the scalability and reconfigurability needed for high-channel-count neural interfaces.
Purpose of the Study:
- To present an architectural framework for a scalable System-on-Chip (SoC) designed for parallel neural signal processing.
- To detail a reconfigurable platform capable of handling massive parallelism in neural recordings.
Main Methods:
- Developed a prototype architecture featuring dual processors and a multi-level reconfigurable platform.
- Integrated functional modules for real-time spike detection and sorting.
- Evaluated performance for a 300-channel neural interface.
Main Results:
- The proposed SoC architecture demonstrates scalability and reconfigurability.
- The platform successfully performs real-time spike detection and sorting for hundreds of neural channels.
- Performance metrics for a 300-channel interface were analyzed.
Conclusions:
- The presented SoC design provides an effective solution for parallel processing of neural signals.
- The reconfigurable architecture supports massive parallelism, crucial for advanced neural recording applications.
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