A 0.0075 mm², 0.0139 FoM Double-Ring Vernier TDC with Vernier Arbiter Phase Calibration and Code Error Cancellation...

This work presents a PET-oriented double-ring Vernier time-to-digital converter (DRVTDC) that targets the timing-quantization block required in multi-voltage-threshold (MVT) and time-over-threshold (ToT) front-end readout for time-of-flight (ToF) positron emission tomography (PET) applications. This work addresses two critical error mechanisms that limit the use of multi-stage Vernier TDCs: parallel output misalignment (POM) between quantization stages and mismatch-induced chasing error (MCE) in the Vernier arbiter array. To suppress these errors, a joint calibration scheme combining code error cancellation (CEC) and Vernier arbiter phase calibration (VAPC) is proposed. The core TDC achieves a 10.4-ps resolution with only 0.0075 mm² core area. The implemented 7-bit coarse counter provides a dynamic range (DR) of 5.12 μs. Empowered by these techniques, the measured DNL and INL ranges are significantly improved from +3.17/-0.89 LSB and +7.0/-6.9 LSB to +0.34/-0.29 LSB and +1.15/-1.09 LSB, respectively, alongside a 26-dB enhancement in the SFDR. The core TDC consumes 1.758 mW, with a total of 5.526 mW including the PLLs.