Current saturation in submicrometer graphene transistors with thin gate dielectric: experiment, simulation, and...

Area of Science:

• Materials Science
• Electrical Engineering
• Solid State Physics

Background:

• Graphene field-effect transistors (FETs) have demonstrated high cutoff frequencies (f(T)) up to 300 GHz.
• However, a significant challenge remains in achieving adequate drain current saturation, which is essential for analog/RF performance.
• Low output conductance (g(ds)) is critical for high intrinsic voltage gain (g(m)/g(ds)) in transistors.

Purpose of the Study:

• To theoretically investigate the impact of dielectric thickness on graphene FET output characteristics.
• To experimentally achieve full drain current saturation in large-scale graphene FETs.
• To demonstrate high intrinsic voltage gain and high-frequency AC performance in optimized graphene FETs.

Main Methods:

• Utilized a surface-potential-based device model for theoretical analysis.
• Fabricated graphene FETs using large-scale chemical vapor deposition (CVD) graphene.
• Employed a very thin gate dielectric layer (equivalent oxide thickness < 2 nm).
• Performed s-parameter measurements to evaluate high-frequency performance.

Main Results:

• Theoretical modeling confirmed the influence of dielectric thickness on output characteristics.
• Experimental results showed full drain current saturation in graphene FETs with ultra-thin dielectrics.
• Achieved a high intrinsic voltage gain of up to 34, comparable to conventional semiconductor FETs.
• Demonstrated high-frequency AC voltage gain and S21 power gain.

Conclusions:

• Ultra-thin gate dielectrics are key to overcoming the current saturation challenge in graphene FETs.
• Optimized graphene FETs exhibit promising performance for analog/RF applications.
• This work paves the way for advanced graphene-based high-frequency electronic devices.